Which statement is true of a pipelined architecture, versus a non-pipelined architecture? Assume a time phase duration of 4 nanoseconds and 5 stages to execute an instruction. Assume the CPU stalls for the minimum possible time during each stall.

Question

BlackTom AI · Accepted Answer

Start by restating the problem to ensure clarity: we are comparing pipelined versus non-pipelined architectures under the given timing parameters—time phase duration of 4 ns, 5 pipeline stages, and stalls during cache misses with a memory access time of 10 ns.
Option a: The claim that the latency of a pipelined CPU will be 5 nanoseconds is incorrect. In a classic 5-stage pipeline, the latency to complete the first instruction (fill the pipeline) is not just a single stage’s time; you must traverse all 5 stages, so the best-case latency per instruction, after the pipeline is filled, is around 5 × 4 ns = 20 ns, assuming no stalls. Thus 5 ns grossly underestimates the startup and steady-state throughput.
Option b: Saying the latency is 4 nanoseconds is also incorrect for the same reason—one stage’s duration, not the full pipeline latency, does not define completion of an instruction. Even in a perfectly balanced pipeline, you still need to pass through all 5 stages to complete one instruction, yielding a larger latency than a single stage duration.
Option c: This option introduces the specific stall scenario but states 10 nanoseconds as the time elapsed to complete the next instruction after a cache miss re-fetch from the first time-phase. In a pipelined design with a cache miss that requires re-fetching, the stall adds overhead beyond just the raw memory access time, and typically the total elapsed time would exceed the simple memory access (and would include the time to re-fill the pipeline). The given 10 ns seems to omit the compounded stall and re-fetch effect described in the problem, making this claim dubious.
Option d: This option also uses the same cache-miss scenario with a 10 ns memory access time, but specifies a total of 30 nanoseconds before the CPU can complete the next instruction after the stall. Given a 5-stage pipeline at 4 ns per stage, the baseline pipeline completion would be 20 ns. If a cache miss forces a re-fetch from the first time-phase, plus the 10 ns memory access, an additional 10 ns of stall time beyond the baseline 20 ns makes 30 ns a plausible total for the stalled completion. This aligns with the described stall behavior and the given timing parameters, making the statement internally consistent with the problem’s assumptions.
Option e: Claiming a 20 nanoseconds total in this scenario would imply an overall stall time of only 0 ns beyond the 20 ns baseline, which contradicts the premise that a cache miss requires memory access and a re-fetch from the first time-phase. Therefore this option underestimates the stall impact and is not consistent with the described mechanism.
In summary, the logic hinges on the pipeline’s baseline latency and the additional stall overhead caused by a cache miss requiring re-fetch from the first time-phase with a 10 ns memory access. The option that coherently combines these elements into a total of 30 ns aligns with the stated assumptions, while the others misstate either the fundamental pipeline latency or the stall cost.

Which statement is true of a pipelined architecture, versus a non-pipelined architecture? Assume a time phase duration of 4 nanoseconds and 5 stages to execute an instruction. Assume the CPU stalls for the minimum possible time during each stall.单项选择题

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